1. Field of the Invention
The present invention relates generally to a through silicon via process, and more specifically to a through silicon via process that forms a passivation layer before an oxide layer is formed on a back side of a substrate.
2. Description of the Prior Art
The through-silicon via technique is quite a novel semiconductor technique. The through-silicon via technique advantages resides mainly in solving the problem of the electrical interconnection of chips, and the TSV belong to a new 3D packing technique field. The hot through-silicon via technique creates products that fit better the market trends of “light, thin, short and small devices” through through-silicon via 3D stacking, in order to provide micro electronic mechanic system (MEMS), photoelectronics and electronic elements with packing techniques of wafer-level package.
The through-silicon via technique drills holes in the wafer through etching or using laser then fills the holes with conductive materials such as copper, polysilicon or tungsten to form vias, i.e. conductive channels connecting inner regions and outer regions. Finally, the wafer or the die is thinned to be stacked or bonded together to be a 3D stack IC. In this way, the wire bonding procedure maybe omitted. Using etching or laser techniques to form conductive vias not only avoids the wire bonding step but also reduces the occupied area on the circuit board and the volume to be packed.
The inner connection distance of the package of the 3D stack IC with the through-silicon via technique, i.e. the thickness of the thinned wafer or the die, is much shorter compared to the conventional stack package of wire bonding type, so the 3D stack IC performs better in many ways, for it has a smaller electrical resistance, a faster transmission, a lower noise and better performances. For the CPUs, flash memories and memory cards especially, the advantages of the shorter inner connection distances of the through-silicon via technique are much more outstanding. In addition, the package size of the 3D stack IC is equivalent to the size of the dice, so the through-silicon via technique is more valuable in portable electronic devices.
In a through silicon via process, a wafer must be fixed in an apparatus as processes, such as aforesaid filling the conductive material in vias processes, are performed on the wafer, wherein the wafer may be fixed by vacuum or electrical voltage etc. However, due to the thickness of an oxide layer on a back side of the wafer approaching 1 microns (μm), the wafer is not easy to be fixed on apparatuses, such as an apparatus of E-chuck. Even though the vacuum or the electrical voltage is increased to fix the wafer on the apparatus, incomplete dechucking, shifting, down transferring or popping of the wafer will still occur.